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September 2006 rev 0.1 Low Power Peak EMI Reducing clock synthesizer
Features
* * * * * * * * Generates a 4x low EMI clock at the output Input frequency: 25 MHz Integrated loop filter components. Frequency deviation: 0.25% (Typ) center spread Operates with a 3.3V Supply. Low power CMOS design. Available in 8-pin SOIC package. Pin compatible with ICS 341-22
PCS3P7101A
Product Description
The PCS3P7101A is a low cost, single-output, clock synthesizer. The PCS3P7101A generates a 4x output clock from a 25 MHz standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving valuable board space and cost. The device employs Spread Spectrum technique to reduce system electro-magnetic interference (EMI). The device also has a power-down feature that tri-state the clock output and turns off the PLL when the PD pin is taken low.
Block Diagram
VDD PD
Modulation XIN/CLKIN XOUT Crystal Oscillator Frequency Divider Feedback Divider Phase Detector Loop Filter
PLL
VCO
Output Divider ModOUT
VSS
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.1
Pin Configuration
CLKIN/XIN 1 VDD 2
8 XOUT
PCS3P7101A
7
PD
PCS3P7101A
VSS 3 NC 4
6 NC 5 ModOUT
Pin Description Pin # Pin Name
1 2 3 4 5 6 7 8 CLKIN/XIN VDD VSS NC ModOUT NC PD XOUT
Type
I P P O I O
Description
Crystal connection or external reference frequency input. This pin has dual functions. It can be connected either to an external crystal or to an external reference clock. Power supply for the entire chip. Ground connection No Connection Spread spectrum low EMI 4x clock output. No Connection Powers down entire chip. Tri-states CLK outputs when low. Has an Internal pull-up resistor. Crystal connection. If using an external reference, this pin must be left unconnected
Absolute Maximum Ratings Symbol
VDD, VIN TSTG TA Ts TJ TDV Storage temperature Operating temperature
Parameter
Rating
-0.5 to +4.6 -65 to +125 0 to +70 260 150 2
Unit
V C C C C KV
Voltage on any pin with respect to Ground
Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD 22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Recommended Operating Conditions1 Parameter
Supply voltage, VDD Low-level input voltage, VIL High-level input voltage, VIH High-level output current, IOH Low-level output current, IOL VDD = 3.15V to3.45V VDD = 3.15V to3.45V VDD = 3.15V to3.45V VDD = 3.15V to3.45V
Min
3.15 2 0
Typ
3.3 -
Max
3.45 0.8 12 12 70
Unit
V V V mA mA C
Operating free-air temperature, TA
Note:1 Unused inputs must be held high or low to prevent them from floating.
Low Power Peak EMI Reducing clock synthesizer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.1
DC Electrical Characteristics Symbol Parameter
VIL VIH IIL IIH VOL VOH IDD ICC VDD ZOUT CIN RPD RPUP Input low voltage Input high voltage Input low current Input high current Output low voltage (VDD = 3.3 V, IOL = 12 mA) Output high voltage (VDD = 3.3 V, IOH = 12 mA) Static supply current* Dynamic supply current (3.3V, 25MHz and no load) Operating voltage Output impedance
PCS3P7101A
Min
VSS - 0.3 2.0 2.4 3.15 -
Typ
50 TBD 3.3 20
Max
0.8 VDD + 0.5 -35 35 0.4 _ 3.45 -
Unit
V V A A V V uA V
Input Capacitance Internal pull-up resistor PD CLK output
4 250 525
pF
K k
* XIN/CLKIN pin and PD pin are pulled low
AC Electrical Characteristics for 3.3V Supply Symbol
CLKIN/XIN ModOUT Input frequency Output frequency Output rise time (measured from 0.8 to 2.0V) Output fall time (measured at 2.0V to 0.8V)
Parameter
Min
40 -
Typ
25 100 1 1 4 4 0 TBD TBD 50 TBD
Max
10 7 60 -
Unit
MHz MHz nS nS mS mS ppm pS pS % pS
tLH* tHL*
tPU tON
Power-up time( PLL lock time from power-up)
Power-up time (first locked cycle after power-up)**
Synthesis Error(Output Frequency) tJC tJP tD tja
Jitter (cycle to cycle)
Period Jitter
Output duty cycle
Maximum Absolute Jitter
*tLH and tHL are measured into a capacitive load of 15pF ** VDD and XIN/CLKIN input are stable, PD pin is made high from low.
Low Power Peak EMI Reducing clock synthesizer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.1
Typical Crystal Oscillator Circuit
PCS3P7101A
R1 = 510
C1 = 27 pF
C2 = 27 pF
Typical Crystal Specifications Fundamental AT cut parallel resonant crystal
Nominal frequency Frequency tolerance Operating temperature range Storage temperature Load capacitance Shunt capacitance ESR 25MHz 50 ppm or better at 25C -25C to +85C -40C to +85C 18pF 7pF maximum 25
Low Power Peak EMI Reducing clock synthesizer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.1
PCS3P7101A
Package Information
8-Pin SOIC Package
E
H
D
A2
A
e B A 1
C L
D
Dimensions Symbol Min Inches Max
Millimeters
Min Max
A1 A A2 B C D E e H L
0.004 0.053 0.049 0.012 0.007
0.010 0.069 0.059 0.020 0.010
0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0
0.25 1.75 1.50 0.51 0.25
0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0 0.050 8
1.27 8
Low Power Peak EMI Reducing clock synthesizer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.1
Ordering Information Part Number
PCS3P7101AG-08SR PCS3P7101AG-08ST
PCS3P7101A
Marking
3P7101AG 3P7101AG
Package Type
8-Pin SOIC, TAPE & REEL, Green 8-Pin SOIC, TUBE, Green
Temperature
Commercial Commercial
Device Ordering Information
PCS3P7101A
G-08
SR
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent Nos 5,488,627 and 5,631,920.
Low Power Peak EMI Reducing clock synthesizer
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.1
PCS3P7101A
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Part Number: PCS3P7101A Document Version: v0.1
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
Low Power Peak EMI Reducing clock synthesizer
Notice: The information in this document is subject to change without notice.
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